1. Field of the Invention
The present invention relates to an LSI design system through model creation for a functional block for executing logical synthesis, automatic layout and wiring from a hardware description language (HDL), and an LSI design method therefor.
2. Description of the Related Art
The LSI design method to which the present invention relates uses a logical synthesis tool especially for circuit design and an automatic layout tool for layout and wiring.
Since such an LSI design method generally uses languages such as verilog or VHDL in which functions are represented as text-based RTL description and circuits are automatically created through logical synthesis, it is not necessary to perform manual design on a circuit diagram basis. This enables a substantial reduction in TAT (Turn Around Time: time for design and development) in circuit design and a substantial, improvement in quality in the face of larger scale LSIs. Additionally, the LSI design method has other advantages such as easy application to other products since it allows technology-independent design. Layout or wiring can be performed by interfacing the automatically created circuits as a netlist to the automatic layout tools.
However, the larger scale of LSIs in recent years has increased the TAT for logical synthesis and layout or wiring. In this situation, it is required to estimate a chip size and to improve a critical path in early stages of design.
To satisfy these requirements, JP-A-7-288777, for example, proposes a design support apparatus which, in RTL description for circuit design for designing data path sections and control sections in a circuit as separate blocks in terms of layout, executes schematic design in a block with a plurality of layout schemes to accurately estimate the area of the circuit and operational speed.
The approach disclosed in the aforementioned prior art literature shown in FIG. 1, however, does not have a configuration for executing model creation directly from RTL description for a functional block.
For this reason, the area of circuit and operational speed can not be estimated unless layout design is executed at the level of primitive cells (INV, AND, OR or the like) within a functional block.
Additionally, since the quality of a netlist (information on circuit connection) is substantially affected by the degree of completion of a hardware description language (HDL), the estimated area is greatly increased or decreased if a functional block has a smaller degree of completion.
As a result, there exists a disadvantage that the TAT before the estimation of the area of circuit and operational speed is increased which makes it difficult to estimate them in the early stages of design.
It is a main object of the present invention to provide an LSI design system through model creation for a functional block which directly creates a delay model and an area model for a floorplan from an HDL in functional blocks without depending on the degree of completion of the HDL, executes the floorplan and static delay analysis in early stages, and knows and improves a chip size and critical path in early stages of design, and an LSI design method therefor.
The LSI design system through model creation for a functional block according to the present invention comprises an HDL description for a functional block described in an HDL (Hardware Description Language); model creating means for creating a delay model and an area model from the HDL description; a library of the delay model in functional blocks having information on a delay path defined with an outline of the functional block serving as its boundary and having an input, output, and input/output terminal serving as its starting point and ending point; a library of the area model in functional blocks having area information for a functional block estimated from technology-independent logical information, terminal information, and wiring prohibited position information; floorplan means for arranging the area model in an intended chip size frame and carrying out wiring thereof, and estimating validity for the chip size and extracting wiring RC information of resistance and parasitic capacitance of wiring around the area model at the same time; the wiring RC information extracted by the floorplan means; and static timing analyzing means for extracting critical paths at a chip level with a CAD tool by using the delay model and the wiring RC information.
The model creating means may include conversion processing means for converting the HDL description for a functional block into a technology-independent; logical structure; an area information table not having area information of cells of all primitive circuits provided for each technology, but having average values of areas of the cells classified based on types of the cells and the number of input pins and output pins; a delay information table having delay values from a pin to another pin in a connection relationship, the values being average values of delays in cells classified based on the number of pins similarly to the area information table; and modeling means for executing modeling from the logical structure converted by the conversion processing means, the area information table, and the delay information table into the area model and the delay model. The modeling means for modeling into the area model may have means for obtaining the area model using an area value extended at a specified rate from the total area of respective circuits in the technology-independent logical structure in consideration of wiring region in the model. The modeling means for modeling into the delay model may have means for modeling a critical path delay from an input pin of a functional block through a combination circuit to a DFF as a setup time for the input pin of the functional block, a critical path delay from a DFF through a combination circuit to an output pin as a delay time from a clock to the output pin of the functional block, and a critical path delay from an input pin through a combination circuit to an output pin as a delay time from the input pin to the output pin.
The modeling means for modeling into the area model may have means for directly providing an area value to create an area model.
A LSI design method for the LSI design system through model creation for a functional block comprises the steps of: describing the HDL description; creating the delay model and the area model from the HDL description with the model creation means; arranging the area model in an intended chip size frame and carrying out wiring thereof, and estimating validity for the chip size and extracting wiring RC information of resistance and parasitic capacitance of wiring around the area model at the same time with the floorplan means; and extracting critical paths at a chip level with a CAD tool by using the delay model and the wiring RC information with the static timing analyzing means.
The step of creating the delay model and the area model may include the steps of: converting the HDL description for a functional block into a technology-independent logical structure with the conversion processing means; and executing modeling from the logical structure converted by the conversion processing means, an area information table, and a delay information table into the area model and the delay model with the modeling means. The area information table may not have area information of cells of all primitive circuits provided for each technology, but may have average values of areas of the cells classified based on types of the cells and the number of input pins and output pins. The delay information table may have delay values from a pin to another pin in a connection relationship, the values being average values of delays in cells classified based on the number of pins similarly to the area information table. The step of modeling into the area model may have the step of obtaining the area model using an area value extended at a specified rate from the total area of respective circuits in the technology-independent logical structure in consideration of wiring region in the model. The step of modeling into the delay model may have the step of modeling a critical path delay from an input pin of a functional block through a combination circuit to a DFF as a setup time for the input pin of the functional block, a critical path delay from a DFF through a combination circuit to an output pin as a delay time from a clock to the output pin of the functional block, and a critical path delay from an input pin through a combination circuit to an output pin as a delay time from the input pin to the output pin.
The step of modeling into the area model may have the step of directly providing an area value to create an area model.
The present invention is characterized in that it provides a method for estimating a chip size and improving a critical path in early stages in an LSI design method for executing logical synthesis, automatic layout and wiring from a conventional hardware description language (HDL) divided for functional blocks.
Accordingly, since delay model 3 and area model 4 in functional blocks with no limitation to their scale are processed as a library, the number of libraries is extremely reduced, for example, as compared to the case of using a netlist in primitive functions such as INV, AND, OR, thereby reducing the TAT for processing for floorplan 5 and static timing analysis 7.
Therefore, it is easy to estimate a chip size and improve a critical path in early stages of design.
Additionally, it is possible to easily select among a plurality of architectures while models for only one functional block are replaced.
Furthermore, since an area value can be manually inputted or a rate at which an estimated value is increased can be specified in creating the area model, the quality of the floorplan is not dependent on the degree of completion of the HDL, and in extreme cases the chip size can be estimated in early stages of design without an HDL.